A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, e.g., FETs, having feature sizes as small as possible. Many present processes employ features, such as gate electrodes and interconnects, which have less than a 0.18 μm critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. In some cases, these semiconductor devices are electrically isolated from each other by an STI feature.
A conventional STI feature is fabricated by forming a barrier oxide layer of SiO2 over a semiconductor substrate. Next, a nitride layer is formed over the barrier oxide layer. Then, apertures are formed in the nitride layer and the barrier layer to expose a surface of the semiconductor substrate. Following the formation of a shallow trench in the surface of the semiconductor substrate, an oxide deposition is performed. The oxide deposition process forms a field oxide layer (trench oxide) that fills the shallow trench and apertures. In some cases, a liner oxide layer is formed interposed between the trench oxide and the semiconductor substrate. Finally, the nitride layer is stripped from the barrier oxide layer with one or more suitable stripping agents. As a result, a portion of the STI feature is left proud of the barrier oxide layer. That is, an undesirable step is formed between the STI feature and the barrier oxide layer. The step contributes to undesirable thickness variations in the surface topography of layers formed subsequently. The thickness variations can affect the characteristics of the subsequently formed layers
For example, a photoresist layer used in a photolithography process to form precise lines is adversely affected by the topography of the surface. Likewise, the characteristics of an anti-reflective coating (ARC) layer are degraded by significant changes in thickness of the ARC layer. Accordingly, the operability of the device is adversely affected. Further, the reliability and lifetime of the semiconductor device may be degraded. Additionally, the thickness variations may require additional process steps to be accomplished to ensure the semiconductor device is operating within design specifications.
Therefore, a need exists for a method which will produce an STI feature including a surface that is co-planar with an adjacent surface. That is, there is a need for a method that significantly reduces thickness variations in a surface topography of an intermediate semiconductor structure.